In the field of semiconductor technology, integrated circuits are usually produced by progressive projection of structure patterns, formed on masks, onto a semiconductor wafer coated with a photosensitive resist and a subsequent transferring of the structure pattern into layers respectively arranged underneath the resist. In order to further advance the miniaturization of structure sizes within the structure patterns in semiconductor technology, so-called resolution enhancement techniques (RET) are increasingly being resorted to for the projection. These involve, in addition to illumination methods such as off-axis illumination or structure-specific methods such as optical proximity correction (OPC), primarily innovative mask techniques such as phase masks, for example.
With regard to the resolution that can be achieved on a semiconductor wafer by an exposure device in a projection, the best results are obtained specifically by the type of alternating or chromeless phase masks. Alternating phase masks are particularly suitable for the projection of a dense line-gap pattern formed on such a mask type and having a width ratio of lines to gaps of about 1:1.
However, phase conflicts may occur in the case of the aforementioned types of phase masks. In the case of an exposure, the phase conflicts lead to undesirable, still unexposed resist structures in a photosensitive layer arranged on the semiconductor wafer. With the aid of a second or trimming exposure, the resist structures may subsequently be exposed and removed in a downstream development process.
Trimming masks are known which have light-transmissive openings within a nontransparent chrome layer on a substrate, which openings can be projected onto the resist structures of an alternating or chromeless phase mask which have already been produced by phase conflicts. With the aid of further openings in the chrome layer, it is possible, moreover, to expose further structure elements of a structure pattern having dimensions that are not so small and are thus not critical in the photosensitive layer. In this way, with the aid of a set of two masks with structure patterns coordinated with one another, it is possible to image extremely small dimension-critical structure elements besides larger and therefore less critical structure elements.
Trimming masks are typically formed as dark field masks, i.e., the structure elements to be formed on a wafer are formed as openings in a nontransparent or at least semitransparent layer on the substrate of the mask. The trimming masks are also referred to as secondary masks. Alternating phase masks are generally likewise present as dark field masks.
With the use of the phase masks of the alternating or chromeless type, a comparatively large lithographic process window can be obtained for many structure geometries, for example, of line-gap patterns. A lithographic process window represents the ranges of values of exposure dose and focus which are necessary in the event of a projection onto a wafer for not exceeding a specific structure width tolerance.
However, there are specific structure geometries for this mask type, in particular, line-gap patterns having a very special line-to-width ratio that differs from 1:1, for which, in particular, only a small process window can be obtained even using alternating or chromeless phase masks. In particular, a depth of focus that is too small for application in circuit fabrication is achieved in this case. It is usually the case that such structure patterns cannot be imaged with sufficient quality even by a second exposure with the aid of a trimming mask.
One albeit inadequate solution to the existing problem consists in excluding, as early as during the preparation for the purpose of forming the structure pattern on the mask, those widths of individual structure elements or periods of regular patterns for which only a very small process window may be expected for the structure element, for example, on account of experimental or simulator-based investigations. In order nevertheless to be able to realize the desired structure patterns with their functionality in the later completed integrated circuit, it is thus necessary to create designs which satisfy the exclusion criteria mentioned.
This leads to an increased complexity at least in the design of the component. There may also be limitations in the functionality made possible by the layout. This often also results in an enlargement of the circuit area, which may also result in higher costs for fabrication due to the smaller number of circuits per wafer.